The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device that sets a test mode using a reduced number of external terminals.
In recent years, packages and chip areas of semiconductor integrated circuit devices have been increasingly downsized. A package of a semiconductor integrated circuit device has a plurality of external terminals. To downsize the package, it is desired to reduce the number of external terminals.
FIG. 1 shows a conventional semiconductor integrated circuit device 1 with the function of a clock generator. The device 1 includes a package 2 having eight external terminals X. A crystal oscillator H is connected to a pair of external terminals (oscillator terminals) X0 and X1. The crystal oscillator H and an internal oscillator circuit (not shown) generate a clock signal having a predetermined frequency. The other external terminals X in the device 1 are used as a power supply pin, input and output pins, and the like.
The package 2 contains an IC chip 3. The IC chip 3 has pads 3a connected to the external terminals, and pads 3b specially provided for testing purposes. Before the IC chip 3 is packaged, a tester is connected to a pad 3b for testing, to conduct the operation test of the IC chip 3. The device 1 does not have external terminals specially provided for testing purposes (test terminals). In this way, the package 2 is downsized.
Japanese Laid-Open Patent Publication No. 6-309475 discloses a technique for setting a semiconductor integrated circuit device in a test mode without providing test terminals for setting the test mode. According to this technique, the test mode is set by controlling a waveform of a power supply voltage and detecting a change in the power supply voltage. This technique enables the device after packaging to be set to conduct testing, without requiring the device to have test terminals within its package.